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A fine resolution and process scalable CMOS time-to-digital converter (TDC) architecture is presented. A 6-bit fine resolution TDC design using the new architecture is evaluated for positron emission tomography (PET) imaging application. The TDC architecture uses a hierarchical delay processing structure to achieve single cycle latency and high speed of operation. The fine resolution converter, realized in 130 nm CMOS, is designed to operate over a reference clock frequency of 500 MHz but can be scaled to multi GHz operation through time interleaving. Without external calibration, the TDC is used as a 5-bit fine resolution converter with 4.65 ENOB (effective number of bits). Under this condition, the 6-bit TDC has an INL (integral non-linearity) measurement of less than 1.45 LSB and a DNL (differential non-linearity) measurement of less than 1.25 LSB. With external calibration, a reduction of more than 50% in INL/DNL nonlinearities is demonstrated improving the ENOB to 5.5 bits, pushing the TDC to a 6-bit fine resolution operation. The TDC has a 31 ps timing resolution and power consumption of less than 1 mW. The design is believed to be the fastest and the lowest power consuming fine resolution TDC in the literature.