By Topic

Dynamically Reconfigurable Cache for Low-Power Embedded System

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Liming Chen ; Huazhong University of Science & Technology, China ; Xuecheng Zou ; Jianming Lei ; Zhenglin Liu

The choice of cache configuration impacts the system significantly. Modern embedded systems execute a specific class of applications repeatedly, thus adapting the cache parameters to those few applications can obtain tremendous benefits. We propose the dynamically reconfigurable cache architecture to improve not only overall performance, but also energy consumption for embedded systems. First, we introduce a novel reconfiguration management algorithm (RMA) dynamically detecting phase changes and automatically searching the large space of possible cache configurations for the optimal one. Then, a particular cache organization, cooperating with the RMA, is presented to reconfigure the cache with respect to a three-dimensional space, namely, cache capacity, line size, and associativity. The results of experiments validate the efficiency and accuracy of the RMA by performing simulation on the SPEC CPU2000 embedded system benchmarks. We show that the embedded systems can achieve the compromise between performance and energy using this approach.

Published in:

Third International Conference on Natural Computation (ICNC 2007)  (Volume:5 )

Date of Conference:

24-27 Aug. 2007