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The accelerating need for higher performance, due to complex and real-time applications, has made reconfigurable architectures the best platform for solving such problems. A novel dynamically reconfigurable processing array (RPA) is proposed in this paper. The interconnection network and reconfigurable processing units(RPUs) of RPA can be dynamically reconfigured to arrange different interconnection networks and support different arithmetic representations and bits wide by the configurable word. The RPA with 8times8 coarse-grained RPUs matrix can be organized as SIMD architecture, as well as MIMD architecture. Through the results of the DCT transform and FIR filter algorithms mapping into RPA, RPA performs the multimedia related operations efficiently Based on Charter 0.25 um process standard cell library, the area of RPA is 7times7 mm2 and the critical path delay is 16 ns.