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A Sub-600mV, Fluctuation tolerant 65nm CMOS SRAM Array with Dynamic Cell Biasing

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7 Author(s)
Azeez Bhavnagarwala ; IBM T.J. Watson Research Center, Yorktown Heights, NY 10598, Email: Tel: (914)945-3869 ; Stephen Kosonocky ; Yuen Chan ; Kevin Stawiasz
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Combinations of circuit techniques enabling tolerance to Vtau fluctuations in SRAM cell transistors during read or write operations and significant reductions in minimum operating voltage are reported. Implemented in a 9 Kb times 74 b PDSOI CMOS SRAM array with a conventional 65 nm SRAM cell and an ABIST, these techniques, demonstrate VMIN of 0.58 V and 0.40 V/0.54 V for single and dual VDD implementations respectively. The techniques consume a 10-12% overhead in area, improve performance marginally and also enable over 50% reduction in cell leakage with minimal circuit overhead.

Published in:

2007 IEEE Symposium on VLSI Circuits

Date of Conference:

14-16 June 2007