Skip to Main Content
A 15 μm2 cell 4 Kb electrical fuse memory is designed in 90 nm CMOS using core devices only. The N+ 8-sq asymmetric fuses are used to enhance fuse uniformity, reliability, and aggregate electro-migration. High-gain cascade amplifiers sense small resistance differences to achieve a 2.25 V program voltage in 1 mus. A sufficient design window is derived and verified by using on-chip resistance monitor without area overheads.