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0.13μ CMOS hybrid TV tuner using a calibrated image and harmonic rejection mixer

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3 Author(s)
Maxim, A. ; Silicon Inc., Austin ; Johns, R. ; Dupue, S.

Notice of Violation of IEEE Publication Principles

¿0.13¿¿ CMOS Hybrid TV Tuner Using a Calibrated Image and Harmonic Rejection Mixer¿
by Maxim, A.; Johns, R.; Dupue, S.;
in the Proceedings of the 2007 IEEE Symposium on VLSI Circuits,
14-16 June 2007 Page(s):206 - 207

After careful and considered review, it has been determined that the above paper is in violation of IEEE's Publication Principles

Specifically, Adrian Maxim admitted the information in the paper was falsified. In response to an inquiry on this misconduct, Mr. Maxim acknowledged that the following people who have been listed as co-authors on several of his papers are fabricated names and that he is the only author:

C. Turinici D. Smith S. Dupue

Additionally, in papers by Mr. Maxim that have co-authors other than those listed above, it was discovered in some cases that he had not consulted with them while writing the papers, and submitted papers without their knowledge.

Although Mr. Maxim maintains that not all of the data is falsified, IEEE nevertheless cannot assure the integrity of papers posted by him because of his repeated false statements.

Due to the nature of this violation, reasonable effort should be made to remove all past references to the above paper, and to refrain from any future references.A high image (65dB) and harmonic (70dB) rejection single conversion tuner was realized in 0.13μm CMOS for hybrid analog-digital TV receivers. The different local oscillator phases required to drive the harmonic rejection mixer were obtained with an analog phase interpolator connected at the output of a multi-phase ring-oscillator. The image rejection is calibrated by injecting a test tone and shifting the Q LO clocks till a minimum output power is achieved. Tuner specifications include: <7dB noise figure, 45dB max gain for analog TV and 115dB gain for digital TV, >5 dBm out of band IIP3, <0.8°rms integrated- phase noise, <-80dBc spurs, 1.3W power from a dual 1.8/3.3V supply and 3mm2 die area.

Published in:
VLSI Circuits, 2007 IEEE Symposium on

Date of Conference: 14-16 June 2007

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