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A 14b Low-power Pipeline A/D Converter Using a Pre-charging Technique

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4 Author(s)
Honda, K. ; Shizuoka Univ., Shizuoka ; Zheng Liu ; Furuta, M. ; Kawahito, S.

A pre-charging technique to improve the settling response of pipeline stages is demonstrated in a Mbit pipeline A/D converter (ADC). The prototype ADC fabricated in a 0.25 mum CMOS process consumes 102 mW at 30 MSample/s. Measured SNDR and SFDR are 70.7 dB and 82.8 dB, respectively.

Published in:

VLSI Circuits, 2007 IEEE Symposium on

Date of Conference:

14-16 June 2007