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Skew-Tolerant Global Synchronization Based on Periodically All-in-Phase Clocking for Multi-Core SOC Platforms

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5 Author(s)

A periodically all-in-phase clock generator and a skew-tolerant bus wrapper have been developed for multi-core SOC platforms. The clock generator produces clock frequencies in 81-steps, and the bus wrapper makes possible deterministic data transfer among different frequency clocks even when inter-clock skew is as high as 2 clock cycle times. A combination of the clock generator, the bus wrapper, and loosely balanced global clock distribution serves to ease chip-timing design while maintaining deterministic chip behavior.

Published in:

VLSI Circuits, 2007 IEEE Symposium on

Date of Conference:

14-16 June 2007