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A 200-μV/e- CMOS image sensor with 100-ke- full well capaclty

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6 Author(s)
Adachi, S. ; Texas Instrum. Japan, Inashiki ; Woonghee Lee ; Akahane, N. ; Oshikubo, H.
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A high sensitivity CMOS image sensor without the dynamic range (DR) trade-off has been developed by implementing the small floating diffusion (FD) capacitance in the lateral overflow integration capacitor (CS) embedded pixel circuit. A 1/4-inch VGA chip fabricated through 0.18-μm 2P3M process achieves 200-μV/e- conversion gain with 100-ke- full well capacity, 2.2-e-rms noise floor and 93-dB DR. The S/N ratio degradation at the detection node switch from FD to FD+CS is not visible.

Published in:

VLSI Circuits, 2007 IEEE Symposium on

Date of Conference:

14-16 June 2007