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A 200-μV/e- CMOS image sensor with 100-ke- full well capaclty

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6 Author(s)
Satoru Adachi ; DISP Development, Texas Instruments Japan, 2350 Kihara, Miho, Inashiki, Ibaraki 300-0496, Japan, Tel: +81-29-880-4066, Fax: +81-29-880-3242, E-mail: chiro@ti.com ; Woonghee Lee ; Nana Akahane ; Hiromichi Oshikubo
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A high sensitivity CMOS image sensor without the dynamic range (DR) trade-off has been developed by implementing the small floating diffusion (FD) capacitance in the lateral overflow integration capacitor (CS) embedded pixel circuit. A 1/4-inch VGA chip fabricated through 0.18-μm 2P3M process achieves 200-μV/e- conversion gain with 100-ke- full well capacity, 2.2-e-rms noise floor and 93-dB DR. The S/N ratio degradation at the detection node switch from FD to FD+CS is not visible.

Published in:

2007 IEEE Symposium on VLSI Circuits

Date of Conference:

14-16 June 2007