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The low-power, high-programmability digital hearing aid chip with consideration of human factors is implemented. To achieve the human factored design with low-power consumption, the dual threshold preamplifier and the multi-channel digital signal processor (DSP) are designed. The dynamic range of the dual threshold preamplifier exists from 0.45-V to 0.8-V and dissipates 32-muW from a single 0.9-V supply. The core area of the preamplifier and the DSP are 0.057-mm2 and 0.5-mm2 respectively in a 0.18-mum CMOS technology.