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Dynamic run-time scheduling of design modules in partial reconfigurable (pRTR) platforms have recently become an active area. The pRTR integration in System-on-Chips depends on the efficiency of the technique for scheduling the modules. In this paper, an event based dynamic scheduling technique for hardware emulation is proposed. In consideration of given functional modules (e.g. controller, signal processing parts, memory) of a Design-under-Test (DuT), the emulator is directly scheduled by the run-time behavior of the modules. The events for controlling and reconfiguring the emulator depend on the communication activity of the functional modules itself. A HW/SW based generic emulator environment implemented on a state-of-the-art FPGA platform controls the reconfiguration sequence. The benefits are a decreasing number of run-time reconfigurations and an improved utilization of the FPGA resources of the emulator.