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The reduction of the cumbersome operations of multiplication, division, and powering to addition, subtraction and multiplication is what makes the Logarithmic Number System (LNS) attractive. Addition and subtraction, though, are the bottleneck of every LNS circuit, for which there are implementation techniques that tradeoff area, latency and accuracy. This paper reviews the methods of interpolation, multipartite tables and cotransformation for LNS addition and subtraction, but special focus is given on a novel version of cotransformation, for which a new special case is identified. Synthesis results compare an already published Hardware Description Language (HDL) library for LNS arithmetic that uses only multipartite tables or 2nd-order interpolation against a variation of the same library combined with cotransformation. Exhaustive simulation and a graphics example illustrate that the proposed library has smaller area requirements and is more accurate than the earlier library, at the cost of an increase in the latency of the hardware.