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Digital correlation techniques are used in photon correlation spectroscopy (PCS) experiments to gain information about the diffusion coefficient and thereby the size and distribution of submicron particle structures in fluid media. A new multichannel single chip correlator architecture has been developed, implemented on a FPGA device as a HW/SW partitioned system. A fast hardware front-end combined with a highly optimised, hardware accelerated softcore processor allows the simultaneous processing of up to 32 input channels, each with a time dynamic range 1013. This paper outlines the fundamental algorithmic concepts, the actual correlator implementation as well as the HW/SW design consideration to find an optimal trade-off between system resources and application requirements.