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A Low-Power Multi-Gate FET CMOS Technology with 13.9ps Inverter Delay, Large-Scale Integrated High Performance Digital Circuits and SRAM

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18 Author(s)

This paper presents an in-depth analysis of digital performance of a Multi-Gate FET technology. Ring oscillators with metal gates and undopedfins show an inverter delay of 13.9ps at 1V, the highest performance of a Multi-Gate FET technology reported at 1.9nA off-current/stage. NAND and NOR show significant improvement in delay vs. stack height compared to bulk CMOS. SRAM cells and product-typical critical paths with more than 10k transistors demonstrate the capability for large-scale integration.

Published in:

VLSI Technology, 2007 IEEE Symposium on

Date of Conference:

12-14 June 2007