By Topic

Fermi-level pinning position modulation by Al-containing metal gate for cost-effective dual-metal/dual-high-k CMOS

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

15 Author(s)
Kadoshima, M. ; Semicond. Leading Edge Technol. Inc., Ibaraki ; Sugita, Y. ; Shiraishi, K. ; Watanabe, H.
more authors

We propose here cost-effective gate-first dual-metal/dual-high-k CMOS technology in which Fermi-level pinning is "positively" utilized to reduce threshold voltages for the first time. After systematic investigation on the relation between oxygen vacancies in Hf-based high-k film and electrical characteristics, we concluded that the Fermi-level pinning is unavoidable in principle with a thin EOT, but is a stable phenomenon that should be intentionally utilized. In our proposed method, source of oxygen interstitials (Al) is contained in metal gate material for p-FET, and consequently the flatband voltage is properly modulated by "opposite" Fermi-level pinning due to the oxygen interstitials incorporated into the underlying high-k film after high temperature annealing. It is also noteworthy that this method is simple and cost-effective because the initial high-k films are identical for n-and p-FET but they are automatically converted into dual high-k after the annealing process.

Published in:

VLSI Technology, 2007 IEEE Symposium on

Date of Conference:

12-14 June 2007