Layout-design methodology of 0.246-μm2-embedded 6t-SRAM for 45-nm high-performance system LSIs

We successfully developed a 0.246-μm
²
embedded 6T-SRAM for high performance system LSIs. The 45-nm CMOS platform, which features reversed extension and S/D formation, achieves both high performance logic transistors (TV.) and SRAM integration. To take the worst case of process variations into consideration, cell layout is decided by a novel method using SRAM macros, which include over 100 sorts of parametrically designed cell layouts. As a result, the 0.246-μm
²
SRAM has been successfully developed with 140 mV of static noise margin (SNM) at 0.6 V and V
_ccmin
of 0.9 V.