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Integration Friendly Dual Metal Gate Technology Using Dual Thickness Metal Inserted Poly-Si Stacks (DT-MIPS)

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14 Author(s)
Hyung-Suk Jung ; Samsung Electron. Co. Ltd., Yongin ; Sung Kee Han ; Hajin Lim ; Yun Ki Choi
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We have successfully developed integration friendly dual metal gate process utilizing a dual thickness metal inserted poly-Si stacks (DT-MIPS) structure; poly-Si/TaN/HfON stacks for nMOS and poly-Si/capping metal layer(c-ML)/AlOx/TaN/HfON stacks for pMOS. First, in spite of different metal thickness on n/pMOS, a high-selectivity gate etch process can completely remove metal and HfON layers from the S/D active regions with negligible Si recess in both n/pMOS. Consequently, in both short and long channel devices, n/pMOS Vth values of ~plusmn0.35 V are obtained without counter channel doping. Moreover, excellent drive currents (620/250 muA/um for n/pMOS at Ioff=20 pA/um and Vdd=1.2 V) are obtained without using any mobility enhancement technique. Finally, we confirm that the estimated operation voltages for 10 years lifetime for both nMOS PBTI and pMOS NBTI are well beyond the 1.2 V.

Published in:

VLSI Technology, 2007 IEEE Symposium on

Date of Conference:

12-14 June 2007