By Topic

Improving Yields of High Performance 65 nm Chips with Sputtering Top Surface of Dual Stress Liner

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

9 Author(s)
Huilong Zhu ; IBM Semicond. R&D Center (SRDC), Hopewell Junction ; Daewon Yang ; Kumar, M. ; Colt, John
more authors

This paper presents a simple, effective, and economical method to improve the yield of high performance 65 nm SOI CMOS technology using dual stress nitride liner (DSL) for performance enhancement. Sputtering is used to reduce the complexity caused by DSL boundaries to smooth/trim the top surface of the DSL, which results into a significant yield increase. The perfect yield of 36 Mb 0.65 mum2 SRAM is increased by 25%. The yield for dual-core microprocessors is increased by 33% and for single-core microprocessors by 75%. Yield improvement is explained and sputtering effects on DSL stress and device performance are discussed. This method is in qualification process for product manufacturing.

Published in:

VLSI Technology, 2007 IEEE Symposium on

Date of Conference:

12-14 June 2007