Cart (Loading....) | Create Account
Close category search window

Dependable Integration of Full-Porous Low-k Interconnect and Low-leakage/ Low-cost Transistor for 45nm LSTP Platform

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

24 Author(s)

We present a 45 nm LSTP platform featuring a low-leakage/low-cost transistor and full-NCS/dual damascene Cu interconnects. By applying "MSA + spike-RTA" to annealing process, Ion at Vd=1.2 V are 0.54 mA/um at Ioff=40 pA/mum for nMOS and 0.22mA/um at Ioff=20 pA/mum for pMOS. CV/I performance is fully competitive at Vdd=1.1 V. The RC delay of our fulPNCS with thinned BRM is 14% lower than that of the ITRS 2006 update. The full-NCS has an excellent tolerability to stress migration and a mechanical toughness for wire bonding.

Published in:

VLSI Technology, 2007 IEEE Symposium on

Date of Conference:

12-14 June 2007

Need Help?

IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.