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Metallization of Cu on Parylene-C Film Micro-patterned by Hot-embossing

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4 Author(s)
Sung-Won Youn ; Advanced Manufacturing Research Institute (AMRI), National Institute of Advanced Industrial Science and Technology (AIST), 1-2-1 Namiki, Tsukuba, Ibaraki 305-8564, Japan, Tel: +81-29-861-7849, Fax: +81-29-861-7167, E-mail: ; Akihisa Ueno ; Masaharu Takahashi ; Ryutaro Maeda

The issue of integrating copper with low-dielectric constant (low-k) films for interconnects has been greatly alleviated due to the size reduction of integrated circuits (ICs). This study describes a process for copper micro patterning in parylene-C thin film that combines the hot-embossing and electroplating techniques. The process begins with the deposition of a parylene film on a silicon wafer by a vapor deposition polymerization method. To improve the adhesion of a parylene-C onto a silicon, a silicon wafer was treated using SF6 plasma for 2 min, and spin-coated with an adhesion promoter before parylene deposition. Then, the surfaces of parylene-C films were embossed and subsequently treated by O2 plasma at 2 min to improve the adhesion between the parylene and the Cu/Ta seed layer. Finally, micro-scale gap-filled copper lines with the aspect ratio of 2.5 were electroplated, and the back side of electroplated metal is planarized to the level of the top of the parylene-C layer by a chemical mechanical planarization (CMP) process.

Published in:

Polytronic 2007 - 6th International Conference on Polymers and Adhesives in Microelectronics and Photonics

Date of Conference:

Jan. 16 2007-Yearly 18 2007