Skip to Main Content
The issue of integrating copper with low-dielectric constant (low-k) films for interconnects has been greatly alleviated due to the size reduction of integrated circuits (ICs). This study describes a process for copper micro patterning in parylene-C thin film that combines the hot-embossing and electroplating techniques. The process begins with the deposition of a parylene film on a silicon wafer by a vapor deposition polymerization method. To improve the adhesion of a parylene-C onto a silicon, a silicon wafer was treated using SF6 plasma for 2 min, and spin-coated with an adhesion promoter before parylene deposition. Then, the surfaces of parylene-C films were embossed and subsequently treated by O2 plasma at 2 min to improve the adhesion between the parylene and the Cu/Ta seed layer. Finally, micro-scale gap-filled copper lines with the aspect ratio of 2.5 were electroplated, and the back side of electroplated metal is planarized to the level of the top of the parylene-C layer by a chemical mechanical planarization (CMP) process.