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Dynamic Cache Placement with Two-level Mapping to Reduce Conflict Misses

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3 Author(s)
K. Rajan ; Indian Institute of Science, India ; R. Govindarajan ; Bharadwaj Amrutur

Due to the tight coupling between processor cycle time and L1 access time, L1 caches are typically small and have low associativities. As a consequence they incur a higher percentage of conflict misses than lower level caches. The extent of conflict depends on the memory access pattern exhibited by the program, and can vary from program to program. By using a fixed set of bits to index the cache, conventional mapping enforces the same rigid mapping from address to cache set for all programs. This results in a non-uniform distribution of addresses among cache sets causing unnecessary conflict misses. Such conflicts could be avoided if some flexibility in mapping is exercised.

Published in:

16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007)

Date of Conference:

15-19 Sept. 2007