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Results of analytical and experimental studies of the mechanisms of neutron effects on VLSI structures are described in this paper. The issue of whether a single neutron-produced defect cluster can produce a significant amount of permanent damage ("hard error") in a VLSI cell is addressed. Properties of average defect clusters in silicon are calculated as a function of neutron energy, including dimensions, defect densities, and local electrical properties. The expected effects of a single cluster on MOS and bipolar VLSI geometries are described, and predictions are made of the neutron fluence required to produce a cluster at a critical location in an integrated circuit. Experimental results obtained for 14-MeV neutron-irradiated small-geometry bipolar test chips are described and compared with predictions based on cluster calculations. Much of the present data is accounted for satisfactorily in terms of an average cluster model. The present results suggest that hard errors will occur in VLSI structures at relatively modest neutron fluences. This situation may cause lower bounds to be placed on device sizes for applications requiring radiation tolerance.