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A radiation-tolerant, high-speed, bulk CMOS VLSI circuit design, utilizing a new NMOS structure, has been investigated, based on Â¿-ray irradiation experimental results for 2Â¿m shift registers. By utilizing 60-bit clocked gate and transfer gate static shift register circuits, the usefulness of radiation-hard NMOS structure and circuit design parameter optimization has been confirmed experimentally, showing 50 MHz operation CMOS circuits at 5 V supply voltage after 1 Ã 105 rads (Si) irradiation. The limitations of dynamic circuits in radiation-tolerant circuit designs have also been shown, using 120-bit dynamic shift register circuits. Based on the above results, radiation-tolerant, high-performance, bulk CMOS VLSI circuit designs are discussed.