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Modeling of Single-Event Upset in Bipolar Integrated Circuits

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1 Author(s)
John A. Zoutendyk ; Jet Propulsion Laboratory, California Institute of Technology 4800 Oak Grove Drive, Pasadena, California 91109

The results of work done on the quantitative characterization of single-event upset (SEU) in bipolar random-access memories (RAMs) have been obtained through computer simulation of SEU in RAM cells that contain circuit models for bipolar transistors. The models include current generators that emulate the charge collected from ion tracks. The computer simulation results are compared with test data obtained from a RAM in a bipolar microprocessor chip. This methodology is applicable to other bipolar integrated circuit constructions in addition to RAM cells.

Published in:

IEEE Transactions on Nuclear Science  (Volume:30 ,  Issue: 6 )