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A silicon gate CMOS process on bulk silicon has been developed which can normally be applied to any production circuit and raise its intrinsic hardness to ionizing radiation environments to at least 5 Ã 104 Rads-Si. This is an order of magnitude above the failure level of most commercial CMOS integrated circuits. Dry oxidation of the silicon along with heavy P-well surface concentration is used to obtain this result, with the only penalty being a small increase in gate propagation delay. Both circuit upset and latchup levels are also improved with this radiation-hardened silicon gate CMOS process.