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Modeling Rapid Annealing in Digital Integrated Circuits

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2 Author(s)
Duncan, L.W. ; IRT Corporation San Diego, California 92138 ; Mallon, C.E.

An analytical model for the effects of rapid annealing in narrow base bipolar transistors has been developed. This model utilizes transistor base-emitter voltage and an empirical curve to calculate annealing factor with time. The model has been incorporated into the TRAC circuit analysis code and used to predict the time-dependent response of a low-power Schottky TTL NAND gate and a four-bit shift register as a function of neutron fluence and operating condition.

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Nuclear Science, IEEE Transactions on  (Volume:26 ,  Issue: 6 )