Neutron Damage Annealing in Silicon n-Channel Junction Field Effect Transistors

Annealing of neutron damage has been studied in n-channel, epitaxial silicon JFET's. This study includes measurements of the parameters, gmsat, IDSS, and VPO in devices with various phosphorous concentrations in the channel region. The recovery in device parameters during isochronal annealing exhibits a significant dependence on both the exposure fluence and the phosphorous concentration. The fluence dependence is due to the non-linear relationship between device parameters and defect concentration. The dependence on the phosphorous concentration is thought to be caused by E-center formation and break-up during neutron damage reordering. The recovery observed in the JFET's during annealing occurs at temperatures which are commonly reached during normal operation of power devices. Hence, significant self-healing of damage may occur during operation of such devices.