By Topic

The Design of Derandomizing Buffer Stores for High Data Rates

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Hahn, Jack ; Pegram Nuclear Physics Laboratory Columbia University New York, New York ; Zidon, Amikam ; Gillman, Cyril ; Atzmon, Abraham

Derandomizing buffer stores for parallel digital data, and their applicability when the arrival distribution is Poisson, are discussed. It is shown that resolving time rather than size may typically be the major cause of data loss. A logical design for buffer organization is presented which lends itself to high speed operation. The organization is simple, requires only high speed bistable elements and logical gates, and may be used to design derandomizing buffers out of a variety of electronic devices. The highest speed of operation can be closely predicted as the propagation delay of the bistable device plus two times the propagation delay of the gates used. A number of buffers have been constructed using commercially available integrated circuits. One version has been operated at word rates of 114 mHz. Series-parallel organizations are discussed for use in large buffers operated at the highest speeds.

Published in:

Nuclear Science, IEEE Transactions on  (Volume:16 ,  Issue: 1 )