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A CMOS 15-bit 125-MS/s Time-Interleaved ADC With Digital Background Calibration

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3 Author(s)
Zwei-Mei Lee ; Nat. Chiao-Tung Univ., Hsin-Chu ; Cheng-Yeh Wang ; Jieh-Tsorng Wu

A 15-bit 125-MS/s two-channel time-interleaved pipelined ADC is fabricated in a 0.18 mum CMOS technology, and achieves 91.9 dB SFDR, 69.9 dB SNDR for a 9.99 MHz input. This ADC incorporates a single sample-and-hold amplifier which employs a precharged circuit configuration to mitigate performance requirements for its opamp. Digital background calibration is applied to maintain the conversion linearity of each A/D channel and also correct both gain and offset mismatches between the two channels. Excluding I/O buffers, the chip occupies an area of 4.3 times 4.3 mm2 and dissipates 909 mW from a 1.8 V supply.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:42 ,  Issue: 10 )