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Low-power building blocks for a serial transmitter operating up to 86 Gb/s are designed and implemented in a 130-nm SiGe BiCMOS technology with 150-GHz SiGe fT HBT. Design techniques are presented which aim to minimize high-speed building block power consumption. They include lowering the supply voltage by employing a true BiCMOS high-speed logic family, as well as reducing current consumption by trading off tail currents for inductive peaking. A serial transmitter testchip consuming under 1 W is fabricated and operation is verified up to 86 Gb/s at room temperature (92 Gb/s and 71 Gb/s at 0degC and 100degC, respectively). The circuit operates from a 2.5-V supply voltage, which is the lowest supply voltage for circuits at this data rate in silicon technologies reported to date.