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This paper describes the test and measurement of high-frequency analog/RF cores in a mixed-signal system-on-chip (SoC) environment using an embedded tester core. A new test methodology has been developed in which high-frequency tests are performed on-chip, but the control and test results are transmitted over the lower bandwidth connectivity associated with the SoC I/O terminals. A low-frequency analog signal is used to modulate a high-frequency squarewave and the resulting waveform is applied to a high-frequency circuit-under-test (CUT) as a test stimulus. The CUT's response is sampled using a coherent subsampling technique and the captured samples are transmitted at low-speeds off-chip from the SoC. A coupled phase-locked-loop and delay- locked-loop structure is employed to generate test waveforms in the 2.7-GHz range and to support high-resolution sampling with a sampling resolution of less than 10 ps. Simulation results using a reference low noise amplifier as a CUT shows the effectiveness of the proposed test method. The tester core has been sent for fabrication in CMOS 0.18-mum technology with a target area of 1 mm2.
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on (Volume:26 , Issue: 10 )
Date of Publication: Oct. 2007