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A Statistical Algorithm for Power- and Timing-Limited Parametric Yield Optimization of Large Integrated Circuits

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4 Author(s)
Mani, M. ; Univ. of Texas, Austin ; Devgan, A. ; Orshansky, M. ; Yaping Zhan

Variability in process parameters leads to a significant parametric yield loss of high-performance ICs due to the large spread in leakage-power consumption and speed of chips. In this paper, we propose an algorithm for total power minimization under timing constraints in the presence of variability. The algorithm is formulated as a robust optimization program with a guarantee of power and timing yields, with both power and timing metrics being treated probabilistically. Power reduction is performed by simultaneous sizing and dual threshold-voltage assignment. An extremely fast run-time is achieved by casting the problem as a second-order conic problem and solving it using efficient interior-point optimization methods. The performance of the algorithm was evaluated on a variety of public and industrial benchmarks, with a library characterized using 70-nm Berkeley Predictive Technology Model. When compared to the deterministic optimization, the new algorithm, on average, reduces static power and total power at the 99.9th quantile by 31% and 17%, respectively, without loss of parametric yield. The run-time on the benchmarks is 30times faster than other known statistical power-minimization algorithms.

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:26 ,  Issue: 10 )