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Simultaneous On-Chip Bus Synthesis and Voltage Scaling Under Random On-Chip Data Traffic

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2 Author(s)
Sujan Pandey ; Darmstadt Univ. of Technol., Darmstadt ; Manfred Glesner

This paper presents a statistical approach to synthesize an energy conscious the optimal bus width and the number of buses. The slack is exploited to maximize bus sharing and to reduce energy consumption by simultaneously scaling the voltage during the synthesis of on-chip communication bus. An assumption for bus synthesis is that a system has been partitioned and mapped onto the appropriate modules of a system-on-chip (SoC). Because of the diversity of applications to be run on a single SoC, there exists a variability of data size to be transferred among the on-chip communicating modules. This variability of data size is modeled as a random variable with a known distribution function. The resulting synthesis problem is relaxed to a convex quadratic optimization problem and solved efficiently using a convex optimization tool. The effectiveness of our approach is demonstrated by applying optimization to an automatically generated benchmark and a real-life application. By scaling voltage of a bus, a tradeoff between communication bus cost (bus width and the number of buses) and energy reduction is explored. The experimental results show the significant reduction in communication energy with scaling voltage. However, it offers a limitation to minimize the communication bus cost, if the voltage is scaled beyond its minimum limit. Furthermore, we also estimate the distribution of voltage under a random data size using an analytical method and the Monte Carlo simulation. The results show that the analytically estimated statistical parameters of voltage are close to the simulated results.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:15 ,  Issue: 10 )