Skip to Main Content
Recently, the demand for ultra low-power and low-cost digital design has grown significantly due to the fast growth of battery-operated portable applications. Many such applications need circuits to be fabricated on flexible substrate such as polymer, glass etc. Low Temperature Polycrystalline Silicon Thin Film Transistors (LTPS-TFTs) have been a promising candidate to realize digital circuits on such flexible substrates with low manufacturing cost. Typically, TFT device sizes are large with many high defect grain boundary (GB) regions in the channel. Therefore, they usually operate at high supply (10~20 V) to achieve sufficient current drive ability. Device optimization (i.e, scaling of L, Tox etc) can allow us to reduce the supply voltage for low-power and better performance but that would increase the statistical variations induced by randomly located GBs. Due to polycrystalline material properties, this inherent GB variation is much more significant than the other parametric variations (i.e., L, W and Tox variation). To ensure low power dissipation, good performance and robustness, it is imperative to develop techniques which can predict and minimize the effect of such variations in the circuits. In this work, we explore an efficient design methodology to aggressively reduce the device-to-device variation in LTPS-TFT circuits. First, a response surface method (RSM) is used to accurately predict the statistical variation in LTPS-TFT devices. Our simulation results in 200 nm technology node show that due to the intrinsic variation induced by the random position and orientation of grain boundaries (GBs) in the channel, 61% variation (sigma/mu) in Ion can be observed. Under this assumption, we propose a variation-aware circuit design technique based on the multi-finger parallel (MFP) TFT structure. It is shown that by using our proposed MFP TFT structure, one can reduce the variation (sigma/mu) in Ion by 18%~ 30% with 9%~27% overhead in area.