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This paper presents a whole study of sub-32 nm CMOS 4T SRAM cells in fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar independent self-aligned gates. Both independent-and connected-gate operation is analyzed either with symmetrical or asymmetrical transistors which have been adjusted according to the current process possibilities. An improved 4T driverless (DL) SRAM cell is proposed and compared with a 4T loadless (LL). Both cells take advantage of the back gate to improve stability in read and retention mode by using a feedback between access transistor and opposite storage node. A set of criteria have been analyzed for an efficient characterization of read-, retention-and write margins, power and access time. Typical and worst cases have been computed to assure operating margins in presence of accurate process variation.