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FinFET SRAM Process Technology for hp32 nm node and beyond

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1 Author(s)
Yagishita, A. ; Toshiba Corp. Semicond. Co., Yokohama

Progresses in FinFET SRAM process technology are reviewed. The process technologies discussed in this paper are narrow and uniform fin formation, reduction of source/drain parasitic resistance, gate stack for threshold voltage control, integration scheme to build FinFET and planar FET on a wafer, and fin height tuning technique for beta-ratio control. These technologies are considered to enable the FinFET to become a prospective device for future SoC applications. Furthermore, FinFET future prospects are also presented.

Published in:

Integrated Circuit Design and Technology, 2007. ICICDT '07. IEEE International Conference on

Date of Conference:

May 30 2007-June 1 2007

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