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Accurate estimation of critical path delays in circuits is a challenging task, particularly when variations due to manufacturing are considered. For small circuits (such as standard cells), simulation-based characterisation is preferred for better accuracy. For large circuits, statistical timing analysis techniques are used, but these methods typically yield a pessimistic overestimate. In view of the growing size of custom cell designs, an intermediate approach is required -one that can scale to circuits of moderate size and can produce more accurate estimates than traditional static timing analysis methods. A new method is presented that combines symbolic event propagation with statistical timing analysis and thereby achieves a significant level of accuracy with acceptable computational overhead. The benefits of the new style of analysis over the ISCAS'89 benchmark circuits are demonstrated.