Electronic System Level Models for Functional Verification of System-on-Chip

Modern verification environments based on object-oriented methodology is a system-level solution that manages the process and data for a particular system-on-chip model. These systems give an ability to integrate smaller blocks of design into larger blocks, which may eventually be integrated into a system. That is reason for performing designing and functional verification at a system level, which allow teams to rapidly create large system-on-chip designs by integrating premade blocks. Integrated verification systems used to store and manage huge amount of simulation data. However, when the amount of data is large, it is difficult to analyze and extract information from it. This data can be archived for later use or it can be mined to look for different kind of violations or to get statistical information about the specified design. The paper describes the system-level verification environment for a functional verification system-on-chip models. With the help of novel approach we can easily use opportunities, that system-level modeling gives us, such as: early software validation of the system, performance analysis of the system, transaction-level verification of the project, architectural analysis of system-on-chip (SoC) , power analysis of a chip, searching hardware/software tradeoffs.