Scheduled System Maintenance:
On Monday, April 27th, IEEE Xplore will undergo scheduled maintenance from 1:00 PM - 3:00 PM ET (17:00 - 19:00 UTC). No interruption in service is anticipated.
By Topic

Electronic System Level Models for Functional Verification of System-on-Chip

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Adamov, A. ; Dept. of DAD, Kharkov Nat. Univ. of Radio Electron., Kharkov ; Mostovaya, K. ; Syzonenko, I. ; Melnik, A.

Modern verification environments based on object-oriented methodology is a system-level solution that manages the process and data for a particular system-on-chip model. These systems give an ability to integrate smaller blocks of design into larger blocks, which may eventually be integrated into a system. That is reason for performing designing and functional verification at a system level, which allow teams to rapidly create large system-on-chip designs by integrating premade blocks. Integrated verification systems used to store and manage huge amount of simulation data. However, when the amount of data is large, it is difficult to analyze and extract information from it. This data can be archived for later use or it can be mined to look for different kind of violations or to get statistical information about the specified design. The paper describes the system-level verification environment for a functional verification system-on-chip models. With the help of novel approach we can easily use opportunities, that system-level modeling gives us, such as: early software validation of the system, performance analysis of the system, transaction-level verification of the project, architectural analysis of system-on-chip (SoC) , power analysis of a chip, searching hardware/software tradeoffs.

Published in:

CAD Systems in Microelectronics, 2007. CADSM '07. 9th International Conference - The Experience of Designing and Applications of

Date of Conference:

19-24 Feb. 2007