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A Dynamically Partial-reconfigurable FPGA-based Architecture for Data Processing on Space Solar Telescope

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5 Author(s)
Zhuo Ruan ; Dept. of Elec. and Comp. Eng., Brigham Young University, Provo, USA. zruan@et.byu.edu ; Yuzhang Han ; Hongbo Cai ; Shengzhen Jin
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Under the influence of reconfigurable embedded computing techniques, advanced reliable space computer has been a vital research area for several years. This paper presents a FPGA-based architecture for run-time parallel processing on space solar telescope (SST), a scientific solar-observation satellite. SST is required to process onboard a huge amount of image data observed through multi-channel CCD cameras- around 1728 GB per day, which requires processing speed more than 10,000 MIPS, if an instruction-set-based processor is adopted. Thus, a FPGA-based reconfigurable architecture is proposed to construct SST's computing core for the purpose of multi-channel parallelization and self-healing capability, when running in severely-radiate solar obit. That is, partial reconfiguration can help "heal" single-particle upset errors imposed by space radiation. Our space reconfigurable specimen machine is composed of commercial (off-the-shelf) Xilinx FPGAs (XC2V1000s and XC2V 3000) and 2GB external Flash-RAMs. In general, the whole processing system is a combination of partial reconfigurable DSP clusters and an embedded LEON2 processor, targeting high-performance payload computing and data transmission in outer space; three reconfiguration strategies are utilized to guarantee system reliability and flexibility.

Published in:

2007 International Symposium on Industrial Embedded Systems

Date of Conference:

4-6 July 2007