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High level synthesis is one of the next major steps to improve the hw/sw co-design process. The advantages of high level synthesis are two-fold. At first the level of abstraction is raised and secondly this allows for exploring the design space to a higher degree than on register transfer level. The design space can be explored by applying several kinds of source code transformations like loop unrolling and tree height reduction. Performing design space exploration manually leads to inefficient and inflexible mappings. This work describes the automated design space exploration for area timing trade-offs by utilising evolutionary multi-objective optimisation. Several performance improvements for genetic algorithms are introduced, which target a fast and accurate design space exploration. Finally, the performance of the proposed algorithm is evaluated.