Skip to Main Content
In our previous work, Full Duplex Switched Ethernet was put forward as an attractive candidate to replace the MIL-STD 1553B data bus, in next generation "1S53B"-embedded applications. An analytic study was conducted, using the Network Calculus formalism, to evaluate the deterministic guarantees offered by our proposal. Obtained results showed the effectiveness of traffic shaping techniques, combined with priority handling mechanisms on Full Duplex Switched Ethernet in order to satisfy 1553B-like real-time constraints. In this paper, we extend this work by the use of simulation. This gives the possibility to capture additional characteristics of the proposed architecture with respect to the analytical study, which was basically used to evaluate worst cases and deterministic guarantees. Hence, to assess the real-time characteristics of our proposed interconnection technology, the results yielded by simulation are discussed and average latencies distributions are considered.