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A Hybrid Memory Sub-system for Video Coding Applications

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4 Author(s)
Su-Shin Ang ; Imperial Coll. London, London ; Constantinides, G. ; Luk, W. ; Cheung, P.

This paper introduces a parameterisable, application and platform-independent, hybrid memory sub-system for custom hardware. This memory sub-system consists of a scratchpad memory (SPM) and a custom parallel cache, which exploits data re-use effectively in spite of data dependence. The cache is capable of exploiting spatial locality of memory accesses in two dimensions, making it ideal for video applications. Further, we present a case study involving the Quad-tree Structured Pulse Code Modulation (QSDPCM) algorithm, commonly used in MPEG applications. Specifically, the data dependent nature of memory accesses is demonstrated. Using the memory sub-system, performance improvements of up to 1.7times and 1.4times are obtained when the application is implemented on an Altera Stratix 2 chip and a Xilinx Virtex 2 chip respectively, compared to a SPM implementation. In addition, memory savings of up to 3.2times are achieved. These results emphasize the importance of developing dynamic memory sub-systems for custom hardware applications.

Published in:

Field-Programmable Custom Computing Machines, 2007. FCCM 2007. 15th Annual IEEE Symposium on

Date of Conference:

23-25 April 2007

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