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Design and Analysis of a New Self-Testing Adder Which Utilizes Polymorphic Gates

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1 Author(s)
Sekanina, L. ; Brno Univ. of Technol., Brno

This paper describes a new self-testing 1-bit full adder. This circuit consists of three polymorphic NAND/NOR gates, two XOR gates and two inverters. The adder is able to detect a reasonable number of stuck-at-faults without the need of any additional logic and diagnostic signals. A fault is indicated by oscillations at the carry-out output. Properties of n-bit carry-propagate adder which is composed of the proposed 1-bit self-testing adders are investigated.

Published in:

Design and Diagnostics of Electronic Circuits and Systems, 2007. DDECS '07. IEEE

Date of Conference:

11-13 April 2007