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A Single-Pair Serial Link for Mobile Displays With Clock Edge Modulation Scheme

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5 Author(s)

A low-power, single-channel clock-edge modulated serial link has been fabricated in a standard 0.18-mum CMOS technology. The link core size is 343 times 188 mum2 for the transmitter and 173 times 83 mum2 for the receiver. The link consumes 3.12 mW when operating at 270 Mb/s with a 1.2-V supply. The proposed link transfers all necessary signals between a graphic processor and a mobile display device over a single pair channel, thereby greatly saving the power and cost of the existing full swing parallel lines. The proposed clock edge modulation (CEM) encoding can keep the channel DC-balanced without an additional bit overhead. Since a clock edge is present for each bit, an external reference clock is not needed and its operating frequency can be varied without the possibility of harmonic locking typically found in a referenceless clock and data recovery circuit. A simple DLL-based CEM decoder is described that recovers the data with low power consumption and high jitter tolerance. An analysis of the jitter tolerance to sinusoidal jitter is included along with measured data. The measurement results show jitter tolerance of 20 UIP-P with 1-MHz sinusoidal jitter. The use of a push-pull voltage-mode driver further reduces the power consumption.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:42 ,  Issue: 9 )