By Topic

Temperature Study of Sub-Micrometric ICs by Scanning Thermal Microscopy

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

10 Author(s)
Gomes, S. ; Univ. Claude Bernard Lyon 1, Villeurbanne ; Chapuis, P.-O. ; Nepveu, F. ; Trannoy, N.
more authors

Surface temperature measurements were performed with a scanning thermal microscope mounted with a thermoresistive wire probe of micrometric size. A CMOS device was designed with arrays of resistive lines 0.35 mum in width. The array periods are 0.8 mum and 10 mum to study the spatial resolution of the SThM. Integrated circuits (ICs) with passivation layers of micrometric and nanometric thicknesses were tested. To enhance signal-to-noise ratio, the resistive lines were heated with an ac current. The passivation layer of nanometric thickness allows us to distinguish the lines when the array period is 10 mum. The results raise the difficulties of the SThM measurement due to the design and the topography of ICs on one hand and the size of the thermal probe on the other hand.

Published in:

Components and Packaging Technologies, IEEE Transactions on  (Volume:30 ,  Issue: 3 )