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A quantitative study on the endurance of an embedded Flash memory with 2T-FNFN device architecture in a 0.13-mum technology node has been presented in this paper. Physical insights of 2T-FNFN device degradation have been obtained through stressing and characterizing large parallel arrays of flash transistors (with floating gate connected). Experiments are carried out on large random accessible arrays based on the 2T-FNFN cells, at a wide temperature range and with different program/erase (P/E) voltages. An empirical model has been developed to describe the temperature-dependent degradation of the program window. This model fits the experimental data over the whole temperature range, and the endurance performance with single-shot P/E cycles exceeds 1 million cycles. This paper provides a method for flash endurance characterization and modeling.