A Simulation Study of the Switching Times of 22- and 17-nm Gate-Length SOI nFETs on High Mobility Substrates and Si

The switching times of ultrathin body semiconductor-on-insulator n-channel field-effect transistors with 22- and 17-nm gate lengths are simulated, and the results obtained for four high mobility substrates (Ge, GaAs, InP, and In
_0.53
Ga
_0.47
As) are compared to Si. Both intrinsic and extrinsic device structures are simulated, and a detailed accounting of device behavior is given. The most important assumptions in this paper are as follows: 1) All devices meet a 270-nA / mum leakage specification at V
_DD
= 1 V, including band-to-band tunneling, and 2) an ideal gate insulator is posited which obtains negligible gate leakage and surface scattering for all semiconductors. From the extrinsic device results, it is found that, at a 22-nm gate length, switching times for the semiconductors considered vary, at most, by a factor of two, while at 17 nm, they vary by, at most, a factor of 2.5; in both cases, In
_0.53
Ga
_0.47
As provides the best switching time, and Si, the worst switching time.