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In this paper, we present a synthesis technique targeted toward coarse-grained antifuse-based field- programmable gate arrays (FPGAs). A macrologic cell, in this class of FPGAs, has multiple inputs and multiple outputs. A library of small logic cells can be generated from this macrocell and used to map the target netlist. First, we calculate the minimum number of macrologic cells required to map a given circuit by using either a dynamic programming or a linear programming technique. Given this minimum number of macrologic cells, we introduce an interconnect-aware clustering algorithm that assigns logic cells to individual macrocells so as to minimize the routing costs. Alternatively, a timing slack-driven clustering algorithm is presented where timing criticalities of nodes in a network are calculated and used to determine the final packing into the macrocells so as to minimize the number of the macrocells on the critical paths. When compared to results from a commercial tool, our two synthesis techniques reduce the number of macrologic cells by 12% and the maximum depth by 35%, respectively.