Skip to Main Content
In this article, we evaluate the impact of idle-cycle insertion on yield by quantifying the number of test escapes. We empirically quantify false failures resulting from IR drop by inserting idle cycles at appropriate points during the scan test application protocol. Launch delay (LD) test delays the launch clock by inserting a certain amount of time (called idle cycles or idle time) after the last shift cycle. During these idle cycles, the chip's power supply network is given time to recover from the IR drop induced by excessive switching activity during scan shifting. The amount of IR drop depends on the power supply network design; different chip designs need different idle times. We present LD test results for two different chip designs: the ELF13 graphics processor and the ELF18 DSP processor.